1. Field
The present disclosure relates generally to an integrated circuit (IC) bus architecture. More specifically, the present disclosure relates to a method and apparatus for power saving and flexible gating in a low power, on-chip bus architecture for interconnecting selectable client circuitry with selected path segments.
2. Background
Integrated circuit bus architectures are designed to interconnect multiple client subsystems (or simply, clients), using a bus so that each client may communicate with another client on the bus. A particular type of bus architecture, referred to as a crossbar (XBAR) architecture, provides a switch topology for allowing select clients to simultaneously access each other. Specifically, these clients may write to and read from the XBAR in an N-way communication scheme, where multiplexing is used to sample specific clients on a cycle-by-cycle basis. The multiplexer select circuitry determines which clients can write to the XBAR and which clients can listen to the XBAR.
The use of XBARs is becoming increasingly common for implementing client-to-client connectivity in high-speed circuitry such as communication and graphics processing circuitry. However, operation of XBAR at high frequencies generally involves the use of repeaters and latch repeaters, which increase dynamic power consumption. For communication processing circuitry such as those used for modems in wireless devices, reducing dynamic power consumption is paramount to enabling practical functionality in modern telecommunication standards. Further, the reduction of dynamic power consumption has to be achieved while avoiding increased latency or logic complexity.
Thus, it would be desirable to be able to address the issues identified above to be able to provide significant increased operating time for devices while not reducing performance significantly.